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Mono3D is a custom standard cell library for transistor-level monolithic 3D integration. The cell library has been extracted and fully characterized. All of the required files for synthesis,  placement, and routing are provided. Mono3D consists of two tiers where each tier is based on the 45 nm process design kit FreePDK45 from NCSU.

The pull-down network of each cell (consisting of nMOS transistors) is built within the top tier whereas the pull-up network (consisting of pMOS transistors) is fabricated within the bottom tier. The communication between the two tiers is achieved by  high density monolithic inter-tier vias (MIVs). The bottom tier consists of five metal layers whereas the top tier has 10 metal layers (see Figure 1). An example cell layout is provided in Figure 2. Please see the publications listed below for more details.

Mono3D facilitates future research on various important aspects of 3D monolithic integration such as benchmarking, thermal integrity, design-for-test, and interaction between the manufacturing/device development and the design process.

Figure 1: Cross-section of the Mono3D technology illustrating the 5 metal layers at the bottom tier and 10 metal layers at the top tier, and MIV.

Figure 2: Layout views of a NAND gate in traditional 2D and transistor-level monolithic 3D technology, illustrating the MIVs used to connect the top and bottom tiers.

  1. C. Yan and E. Salman, “Mono3D: Open Source Cell Library for Monolithic 3D Integrated Circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, to appear
    • A comprehensive description of the different versions of the cell library to investigate various physical design tradeoffs as well as chip-level power/performance results of fully placed and routed monolithic 3D ICs with more than 1.5 million gates.

  2. C. Yan, J. Dofe, S. Kontak, Q. Yu, and E. Salman, “Hardware-Efficient Logic Camouflaging for Monolithic 3D ICs,” IEEE Transactions on Circuits and Systems II: Express Briefs, to appear
    • Demonstrates the use of the proposed cell library for hardware security to thwart image analysis based reverse engineering attacks.

  3. C. Yan, S. Kontak, H. Wang, and E. Salman, “Open Source Cell Library Mono3D to Develop Large-Scale Monolithic 3D Integrated Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems, May 2017 (pdf)
    • Describes the primary characteristics of the 3D monolithic cell library and provides physical design details of a large-scale 3D monolithic circuit produced with the proposed cell library.

  4. J. Dofe, C. Yan, S. Kontak, E. Salman, and Q. Yu, “Transistor-Level Camouflaged Logic Locking Method for Monolithic 3D IC Security,” Proceedings of the IEEE Asian Hardware Oriented Security and Trust Symposium, December 2016 (pdf)
    • Represents the use of the proposed cell library for hardware security.