Ph.D. Graduates of the NanoCAS Lab

  1. Dr. Chen Yan
    • Ph.D. 2018
    • First position: GlobalFoundries, Albany, NY
    • Dissertation title: Leveraging Monolithic 3D Integrated Circuit Technology for Emerging Applications (pdf)
  2. Dr. Weicheng Liu
    • Ph.D. 2018
    • First position: NXP Semiconductors, Austin, TX
    • Dissertation title: Low Voltage Clocking Methodologies for Nanoscale ICs (pdf)
  3. Dr. Zhihua Gan
    • Ph.D. 2017
    • Co-advised by Prof. Yi-Xian Qin
    • First position: Nordco, Beacon Falls, CT
    • Dissertation title: Design Methodologies to Manage Switching Noise with Applications to Biomedical Acoustic Systems (pdf)
  4. Dr. Hailang Wang
    • Ph.D. 2016
    • First position: Apple Inc., Cupertino, CA
    • Dissertation title: Enhancing Signal and Power Integrity in Three-Dimensional Integrated Circuits (pdf)

M.S. Graduates (with thesis) of the NanoCAS Lab

  1. Yongwan Park
    • M.S. 2016,
    • First position: PhD student at the University of Maryland, College Park, MD
    • Thesis: Fully Integrated Hybrid Voltage Regulator for Low Voltage Applications (pdf)
  2. Sushil Panda
    • M.S. 2016
    • First position: Dolphin Technology, Santa Clara, CA
    • Thesis: Investigating the Tolerance of Wirelessly Powered Charge-Recycling Logic to Power-Clock Phase Difference Deviations (pdf)
  3. Tasnuva Noor 
    • M.S. 2016
    • First position: Brookhaven National Lab, Upton, NY
    • Thesis:  Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability (pdf)
  4. Mallika Rathore 
    • M.S. 2014
    • First position: Marvell Semiconductor, Boise, ID
    • Thesis: Design and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks (pdf)
  5. Peirong Ji 
    • M.S. 2013
    • First position: SK Hynix , San Jose, CA
    • Thesis: Quantifying the Effect of Local Power Distribution Network and Vias on Power Integrity
  6. Ziqi Zhang 
    • M.S. 2013
    • First position: Marvell Semiconductor, San Jose, CA
    • Thesis: Comparative Analysis of Near-Threshold and Charge Recovery Circuits for Energy Efficiency and Performance (pdf)
  7. Ajay Chandrasekhar 
    • M.S. 2013
    • First position: Imagination Technologies, San Jose, CA
    • Thesis: Critical Length Estimation for TSV-Based 3D Sub/Near-Threshold Circuits (pdf)
  8. Sateja Mungi 
    • M.S. 2013
    • First position: Intel Corporation, Hudson, MA
    • Thesis: Effective Distance Calculations for On-Chip Decoupling Capacitors in 3D ICs (pdf)
  9. Suhas M. Satheesh 
    • M.S. 2012
    • First position: NVIDIA, Santa Clara, CA
    • Thesis: Power Distribution in TSV Based 3D Processor-Memory Stacks (pdf)
  10. Mohammad H. Asgari 
    • M.S. 2011
    • First position: Ph.D. student at Columbia University, NY
    • Thesis: TSV Related Noise Coupling in 3-D Integrated Circuits (pdf)

B.S. Graduates of the NanoCAS Lab

  1. Scott Kontak
    • B.S. 2017, ECE Honors Research and NSF REU scholarship
    • First position: Ph.D. student at Columbia University, NY
    • Research title: Cell Library Development for Monolithic 3D Integration Technology
  2. Xiaoxi Zhang
    • B.S. 2017, ECE Honors Research
    • First position: Signal Integrity Engineer at Intel, Hillsboro, OR
    • Research title: Multi-bit D Flip-Flop Design for Low Swing Clocking
  3. Yongwan Park 
    • B.S. 2015, NSF REU scholarship
    • First position: M.S. student at Stony Brook University, Stony Brook, NY
    • Research title: Enhanced Regulator Topology for Near-Threshold Operation
  4. Shiwei Fang
    • B.S. 2015, ECE Honors Research
    • First position: Ph.D. student at University of North Carolina at Chapel Hill, Chapel Hill, NC
    • Research title: Low Swing TSV Signaling Using Novel Level Shifters with Single Supply Voltage
  5. Sung Jun Yoon 
    • B.S. 2014, URECA fellow
    • First position: Ph.D. student at Texas A&M University, College Station, TX
    • Research title: A Low Power D Flip-Flop Architecture for Low Swing Clock Trees in Advanced CMOS and FinFET Technologies