1) AC Computing for Wirelessly Powered IoT Devices (NSF-CPS, Simons Foundation)
We have developed a charge-recycling based computing paradigm for RF powered applications such as RFIDs, wireless sensor nodes, and future IoT devices. Contrary to existing methods that rely on rectification and regulation, we can directly use the harvested AC signal to power the computational blocks. Our method eliminates the significant power loss due to rectification, particularly at low input power levels. Furthermore, charge-recycling operation is significantly more efficient than conventional static CMOS. Our preliminary results demonstrate more than an order of magnitude increase in energy efficiency. Thus, we can provide significant on-site computational capability, which is highly desirable for RF-powered devices. Furthermore and more interestingly, the unprecedented increase in efficiency brings us closer to utilizing ambient RF power, as we are currently investigating. Our method has direct applications in multiple domains such as IoT security, computational RFIDs, and near-field brain implantable devices.
2) Hardware Security for 3D ICs (NSF-SaTC:STARSS)
3D ICs introduce unique challenges and opportunities for managing multiple aspects of hardware security, as investigated in this research. Our objective is to go beyond the conventional split manufacturing based approaches and treat 3D ICs as stand-alone entities. As such, we would like to identify 3D specific security attacks and develop appropriate countermeasures. For example, we developed a layout-level camouflaging methodology to thwart image analysis based reverse engineering attacks in monolithic 3D ICs. This method was evaluated with a fully placed and routed SIMON core, lightweight block cipher developed by NSA. Our results demonstrate that the monolithic 3D technology is highly effective for circuit camouflaging since both the area and power overheads are eliminated with a slight degradation in timing characteristics.
3) Heterogeneous 3D SoCs (NSF-CAREER)
In this research, we have focused on both through-silicon via (TSV) and monolithic inter-tier via (MIV) based 3D integration technologies. Our primary emphasis has been on physical design methodologies such as robust power delivery (regulators, multi-plane power distribution), low power design techniques (such as plane-level power gating), signal and sensing integrity. We have developed a comprehensive power distribution system for a 3D processor-DRAM stack. We developed analytic models to estimate TSV-to-transistor noise propagation. We have also investigated the use of TSV based heterogeneous 3D ICs for applications in healthcare such as neural recording and stimulation. Specifically, we have demonstrated the benefits related to sensing integrity for a 3D potentiostat designed to sense neurotransmitter concentrations within the brain.
Most recently, we have developed a fully functional and open source PDK and cell library for transistor-level monolithic 3D integration. Using this PDK and library, we benchmarked large-scale circuits (such as 128-point FFT core) to quantify benefits in footprint, power, and timing. We demonstrated the existence of optimum number of routing tracks to obtain the best system-level power and timing characteristics. Our 3D PDK and libraries are available for download to the research community.
4) Low Voltage Clocking (SRC)
In this research, we have transformed low voltage clocking technique into a practical low power design strategy for large-scale industrial circuits. We can achieve significant reduction in clock power without degrading circuit performance (clock frequency, slew, and skew). We developed novel circuits (flip-flops that can reliably operate with low voltage clocks and efficient level-shifters) and algorithms (slew-aware clock tree synthesis, useful skew for gated low voltage clock trees) that are entirely integrated into a conventional digital design flow.
We developed a fully functional tool to synthesize clock trees for large-scale circuits with multiple clock domains. Our tool outperforms commercial vendor tools in clock constraints and overall clock power. As an additional benefit, our tool runs approximately twice as fast. We have evaluated this methodology in a commercial ARM processor (Cortex-A53) with more than 1 million gates. Our results demonstrate up to 48% reduction in clock power (with no performance degradation) at the expense of approximately 15% increase in die area. The increase in die area can be significantly reduced with slightly relaxed clock constraints (e.g. slew). Results of this research have been successfully transferred to semiconductor industry.
5) Front-end Electronics for a Self-Powered Implantable Sensor for Total Knee Replacement (NIH-R21)
Total knee replacement (TNR) is a very common surgery in the US where the annual volume is expected to exceed 1.3 million by 2020. It is highly important to be able to monitor the health of the joint after surgery so that follow-up revision surgeries are avoided. In this research, we develop the ultra-low power implanted electronics for a sensor designed to monitor the load on the joint. The project exhibits unique challenges where the output of the energy harvester behaves both as a data signal to be digitized and a power supply signal to be rectified. We are developing ultra-low power rectification, followed with efficient delta-sigma quantization methods. We are also investigating power management techniques that involve supercapacitors to reach the required power levels.