Our research activities focus on the following two themes and are supported by National Science Foundation (NSF), Semiconductor Research Corporation (SRC), National Institute of Health, Simons Foundation, and  Office of the Vice President for Research at Stony Brook University:

1) Circuit design methodologies for nanoscale CMOS technologies:

Continuous miniaturization of the technology and greater integration levels have changed the classical understanding of the integrated circuit design process. In addition to the traditional design objectives such as speed, power, and area; new design constraints have emerged including signal and power integrityreliability, and robustness. Due to complicated interdependencies and tradeoffs among these criteria, both the design and efficient verification of the system have become significantly more difficult. In this research, we develop efficient yet sufficiently accurate electrical models and analysis methodologies by utilizing a bottom-up approach.  We develop design guidelines and algorithms to enhance system-wide power and signal integrity with special emphasis on energy efficiency and power consumption.

2) Design-centric exploration of the emerging integrated circuit technologies: 

Relying only on traditional technologies to maintain a steady and long term improvement in system level specifications is no longer a practical approach. A wide variety of novel devices, technologies, and circuits are being developed to continue the exponential increase in functional density. An important example of this effort is three-dimensional (3-D) integration where multiple planes are vertically stacked to maintain the growth in device density while simultaneously enhancing functionality and performance.  In this research, we investigate the design implications of various through-silicon via (TSV) and bonding technologies. We develop design methodologies for robust power distribution and to enhance power, signal, and sensing integrity with emphasis on highly heterogeneous 3D systems-on-chip. This research is expected to serve as a bridge between emerging technologies and their circuit/physical level implementation.