Publications

Book_cover9787121250903
Book

Invited Book Chapters

Patents

  1. R. Willing, E. Salman, M. Stanacevic, M. Jain, S. Towfighian, N. A. Hossain, I. Alwatiqbellah, “Self-Powered Load Sensing Circuitry for Total Knee Replacement,” US Patent Pending
  2. E. Salman, M. Stanacevic, T. Wan, Y. Karimi, and Y. Huang, “Ultra Low Power Core for Lightweight Encryption,” US Patent Pending
  3. E. Salman, M. Stanacevic, T. Wan, Y. Karimi, “Radio Frequency Energy Harvesting Apparatus and Method for Utilizing the Same,” US Patent No US10846581B2
  4. C. Sitik, B. Taskin, E. Salman, and W. Liu, “Slew-Driven Clock Tree Synthesis,” US Patent No US10338633B2
  5. A. Dasdan, E. Salman,  F. Taraporevala, and K. Kucukcakar, “Characterizing Sequential Cells Using Interdependent Setup and Hold Times, and Utilizing the Sequential Cell Characterization in Static Timing Analysis,” US Patent No 7,506,293
  6. R. M. Secareanu, O. L. Hartin, and E. Salman, “Apparatus and Method For Reducing Noise in Mixed-Signal Circuits and Digital Circuits,” US Patent No 7,834,428

 Journal Publications

  1. I. Miketic and E. Salman, “PowerID: Using Supply-Side Impedances of Power Delivery Networks as Signatures for Consumer Electronics,” IEEE Transactions on Consumer Electronics, to appear
  2. P. Shukla, V. Pavlidis, E. Salman, A. Coskun, “TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3D Mobile Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, No. 12, December 2023
  3. I. Miketic, K. Dhananjay, and E. Salman, “Covert Channel Communication as an Emerging Security Threat in 2.5/3D Integrated Systems,” Sensors, Vol. 23, No. 4, 2023
  4. K. Dhananjay and E. Salman, “SEAL-RF: SEcure Adiabatic Logic for Wirelessly-Powered IoT Devices,” IEEE Internet-of-Things Journal, Vol. 10, No. 2, pp. 1112-1123, January 2023
  5. K. Dhananjay, V. Pavlidis, A. Coskun, and E. Salman, “High Bandwidth Thermal Covert Channel in 3D-Integrated Multicore Processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 30, No. 11, pp. 1654-1667, November 2022
  6. M. Jain, N. A. Hossain, S. Towfighian, R. Willing, M. Stanacevic, and E. Salman, “Self-Powered Load Sensing Circuitry for Total Knee Replacement,” IEEE Sensors, Vol. 21, No. 20, pp. 22967-22975, October 2021
  7. I. Miketic and E. Salman, “PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse Engineering,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 29, No. 7, pp. 1285-1296, July 2021
  8. K. Dhananjay and E. Salman, “Charge Based Power Side-Channel Attack Methodology for an Adiabatic Cipher,” Electronics, Vol. 10, No. 12, pp. 1438-1454, June 2021
  9. K. Dhananjay, P. Shukla, V. Pavlidis, A. Coskun, and E. Salman, “Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, No. 3, pp. 837 – 843, March 2021
  10. M. Rathore, P. Milder, E. Salman, “Error Probability Models for Voltage-Scaled Multiply-Accumulate Units,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, No. 7, pp. 1665-1675, May 2020
  11. T. Wan, Y. Karimi, M. Stanacevic, and E. Salman, “AC Computing Methodology for RF-Powered IoT Devices,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 5, May 2019
  12. A. Ibrahim, M. Jain, E. Salman, R. Willing, and S. Towfighian, “A Smart Knee Implant Using Triboelectric Energy Harvesters,” Smart Materials and Structures, Vol. 28, No. 2, 2019
  13. W. Liu, C. Sitik, E. Salman, B. Taskin, S. Sundareswaran, and B. Huang, “SLECTS: Slew-Driven Clock Tree Synthesis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27. No 4, pp. 864-874, April 2019
  14. H, Liu, H. Rui, Y. Lu, Y. Wang, E. Salman, and J. Liang, “Boosting the Efficiency of a Footstep Piezoelectric-Stack Energy Harvester by Using the Synchronized Switch Technology,” Journal of Intelligent Material Systems and Structures, Vol. 30, No. 6, 2019
  15. C. Yan, J. Dofe, S. Kontak, Q. Yu, and E. Salman, “Hardware-Efficient Logic Camouflaging for Monolithic 3D ICs,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, No. 6, pp. 799-803, June 2018 (pdf)
  16. C. Yan and E. Salman, “Mono3D: Open Source Cell Library for Monolithic 3D Integrated Circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 3, pp. 1075-1085, March 2018 (pdf)
  17. C. Yan, Z. Gan, and E. Salman, “Package Embedded Spiral Inductor Characterization with Application to Switching Buck Converters,” Microelectronics Journal, Vol. 66, pp. 41-47, August 2017 (pdf)
  18. T. Wan, Y. Karimi, M. Stanacevic, and E. Salman, “Perspective Paper – Can AC Computing be an Alternative for Wirelessly Powered Devices,” IEEE Embedded Systems Letters, Vol. 9, No. 1, pp. 13-16, March 2017 (pdf)
  19. H. Wang and E. Salman, “Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 2, pp. 769-773, February 2017 (pdf)
  20. C. Sitik, W. Liu, B. Taskin, and E. Salman, “Design Methodology for Voltage-Scaled Clock Distribution Networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 10, pp. 3080-3093, October 2016 (pdf)
  21. H. Wang and E. Salman, “Decoupling Capacitor Topologies for TSV-based 3D ICs with Power Gating,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 12, pp. 2983-2991, December 2015 (pdf)
  22. Z. Gan, E. Salman, and M. Stanacevic, “Figures-of-Merit to Evaluate the Significance of Switching Noise in Analog Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 12, pp. 2945-2956, December 2015 (pdf)
  23. C. Sitik, E. Salman, L. Filippini, S. J. Yoon, and B. Taskin, “FinFET-Based Low Swing Clocking,” ACM Journal on Emerging Technologies in Computing Systems, Vol. 12, No. 2, pp. 13:1-13:20, August 2015 (pdf)
  24. P. Ji and E. Salman, “Quantifying the Effect of Local Interconnects on On-Chip Power Distribution,” Microelectronics Journal, Vol. 46, No. 3, pp. 258-264, March 2015 (pdf)
  25. H. Wang, M. H. Asgari, and E. Salman, “Compact Model to Efficiently Characterize TSV-to-Transistor Noise Coupling in 3D ICs,” Integration, the VLSI Journal, Vol. 47, No. 3, pp. 296-306, June 2014 (pdf)
  26. S. M. Satheesh and E. Salman, “Power Distribution in TSV Based 3D Processor-Memory Stacks,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 4, pp. 692-703, December 2012 (pdf)
  27. E. Salman and E. G. Friedman, “Utilizing Interdependent Timing Constraints to Enhance Robustness in Synchronous Circuits,” Microelectronics Journal, Vol. 43, No. 2, pp. 119-127, February 2012 (pdf)
  28. S. Kose, E. Salman, and E. G. Friedman, “Shielding Methodologies in the Presence of Power/Ground Noise,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 8, pp. 1458-1468, August 2011 (pdf)
  29. E. Salman and Q. Qi, “Path Specific Register Design to Reduce Standby Power Consumption,” Journal of Low Power Electronics and Applications, Vol. 1, No. 1, pp. 131-149, April 2011 (pdf)
  30. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, “Methodology for Efficient Substrate Noise Analysis in Large Scale Mixed-Signal Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 10, pp. 1405-1418, October 2009 (pdf)
  31. E. Salman, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, “Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 10, pp. 1559-1564, October 2009 (pdf)
  32. E. Salman, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, “Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance,” IEEE Transactions on Circuits and Systems – I: Regular Papers , Vol. 56, No. 5, pp. 997-1004, May 2009 (pdf)
  33. E. Salman, A. Dasdan, F. Taraporevala, K. Kucukcakar, and E. G. Friedman, “Exploiting Setup-Hold Time Interdependence In Static Timing Analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 6, pp. 1114-1125, June 2007 (pdf)

 Refereed Conference Publications (IEEE / ACM)

  1. K. Dhananjay, V. F. Pavlidis, A. K. Coskun, and E. Salman, “Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors,” IEEE International Symposium on Quality Electronic Design, April 2024
  2. H. Haghshenas, M. Chahari, E. Salman, R. Willing, S. Towfighian, M. Stanaćević, “Power Transfer Optimization for Triboelectric Nanogenerators,” IEEE Biomedical Circuits and Systems Conference, October 2023
  3. A. Abdurrob, E. Salman, J. Lombardi, “Thermal Integrity of ReRAM-based Near-Memory Computing in 3D Integrated DNN Accelerators,” IEEE International System-on-Chip Conference, September 2023
  4. M. Rathore, P. Milder, and E. Salman, “Precision and Performance-Aware Voltage Scaling in DNN Accelerators,” ACM/IEEE Great Lakes Symposium on VLSI, June 2023
  5. I. Miketic, K. Dhananjay, and E. Salman, “Information-Theoretic Perspective to Thermal Covert Channels,” IEEE International Symposium on Circuits and Systems, May 2023
  6. M. Jain, M. Stanacevic, R. Willing, S. Towfighian, and E. Salman, “Wireless Power Transfer for Smart Knee Implants,” IEEE International Symposium on Circuits and Systems, May 2022
  7. K. Dhananjay and E. Salman, “EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel Resistance,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 332-337, July 2021
  8. Z. Zhang, I. Miketic, E. Salman and Q. Yu, “Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 132-137, July 2021
  9. Z. Zhang, I. Miketic, E. Salman and Q. Yu, “Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking,” ACM/IEEE Great Lakes Symposium on VLSI, pp. 415-420, June 2021
  10. P. Shukla, S. S. Nemtzow, V. Pavlidis, E. Salman, and A. Coskun, “Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators,” IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 709-714, January 2021
  11. K. Dhananjay and E. Salman, “Special Session: Adiabatic Circuits for Energy-Efficient and Secure IoT Systems,”  IEEE International Conference on Computer Design, October 2020
  12. Y. Park and E. Salman, “High Efficiency Fully Integrated On-Chip Regulator for Wide-Range Output Current,” IEEE International Symposium on Circuits and Systems, October 2020
  13. I. Miketic and E. Salman, “Energy Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration,” IEEE International System-on-Chip Conference, September 2020
  14. B. Gungor, M. Yazici, E. Salman, and Y. Gurbuz, “Establishing a Covert Communication Channel in RF and mm-Wave Circuits,” IEEE International Midwest Symposium on Circuits and Systems, August 2020
  15. M. Jain, N. A. Hossain, S. Towfighian, M. Stanacevic, and E. Salman, “System Prototype for a Triboelectric Harvester in a Smart Knee Implant,” SPIE Active and Passive Smart Structures and Integrated Systems IX, April 2020 (finalist for the best paper award)
  16. M. Jain, A. Ibrahim, E. Salman, M. Stanacevic, R. Willing, and S. Towfighian, “Frontend Electronic System for Triboelectric Harvester in a Smart Knee Implant,” IEEE International Midwest Symposium on Circuits and Systems, August 2019
  17. P. Shukla, A. Coskun, V. Pavlidis, and E. Salman, “An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs,”  ACM/IEEE Great Lakes Symposium on VLSI, May 2019
  18. C. Sitik, W. Liu, B. Taskin, and E. Salman, “Low Voltage Clock Tree Synthesis with Local Gate Clusters,” ACM/IEEE Great Lakes Symposium on VLSI, May 2019
  19. I. Miketic and E. Salman, “Power and Data Integrity in Monolithic 3D Integrated SIMON Core,” IEEE International Symposium on Circuits and Systems, May 2019
  20. T. Noor and E. Salman, “A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability,” IEEE International Symposium on Circuits and Systems, May 2019
  21. Y. Huang, T. Wan, E. Salman, and M. Stanacevic, “Signal Shaping at Interface of Wireless Power Harvesting and AC Computational Logic,” IEEE International Symposium on Circuits and Systems, May 2019
  22. M. Rathore, P. Milder, and E. Salman, “Towards TFET based Approximate Computing for Deep Learning,” Government Microcircuit Applications & Critical Technology Conference, March 2019
  23. I. Miketic and E. Salman, “Monolithic 3D Integrated Encryption Core,” Government Microcircuit Applications & Critical Technology Conference, March 2019 (pdf)
  24. A. Ibrahim, M. Jain, E. Salman, R. Willing, and S. Towfighian, “Feasibility of Triboelectric Energy Harvesting and Load Sensing in Total Knee Replacement,” The ASME Conference on Smart Materials, Adaptive Structures and Intelligent Systems, September 2018
  25. E. Salman, M. Stanacevic, S. Das, and P. Djuric, “Leveraging RF Power for Intelligent Tag Networks,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 329-334, May 2018 (pdf)
  26. T. Wan and E. Salman, “Ultra Low Power SIMON Core for Lightweight Encryption,” Proceedings of the IEEE International Symposium on Circuits and Systems, May 2018 (pdf)
  27. M. Rathore and E. Salman, “Error Probability Models to Facilitate Approximate Computing in TFET based Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems, May 2018 (pdf)
  28. C. Yan and E. Salman, “Physical Design of Monolithic 3D ICs with Applications to Hardware Security,”  Government Microcircuit Applications & Critical Technology Conference, pp. 702-707, March 2018 (pdf)
  29. T. Wan, E. Salman, and M. Stanacevic, “AC Computing Methodology for RF Powered IoT Security,” Government Microcircuit Applications & Critical Technology Conference, pp. 939-944, March 2018 (pdf)
  30. C. Yan and E. Salman, “Routing Congestion Aware Cell Library Development for Monolithic 3D ICs,” Proceedings of the IEEE International Conference on Rebooting Computing, November 2017 (pdf)
  31. C. Yan, S. Kontak, H. Wang, and E. Salman, “Open Source Cell Library Mono3D to Develop Large-Scale Monolithic 3D Integrated Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2581-2584, May 2017 (pdf)
  32. T. Wan, Y. Karimi, M. Stanacevic, and E. Salman, “Energy Efficient AC Computing Methodology for Wirelessly Powered IoT Devices,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 509-512, May 2017 (pdf)
  33. C. Yan, Z. Gan, and E. Salman, “In-Package Spiral Inductor Characterization for High Efficiency Buck Converters,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2396-2399, May 2017 (pdf)
  34. J. Dofe, Z. Zhang, Q. Yu, C. Yan, and E. Salman, “Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits,”  Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 327-332, May 2017 (pdf)
  35. J. Dofe, C. Yan, S. Kontak, E. Salman, and Q. Yu, “Transistor-Level Camouflaged Logic Locking Method for Monolithic 3D IC Security,” Proceedings of the IEEE Asian Hardware Oriented Security and Trust Symposium, December 2016 (pdf)
  36. J. Dofe, Q. Yu, H. Wang, and E. Salman, “Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 69-74, May 2016 (pdf)
  37. T. Wan, E. Salman, and M. Stanacevic, “A New Circuit Design Framework for IoT Devices: Charge Recycling with Wireless Power Harvesting,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2046-2049, May 2016 (pdf)
  38. Y. Park and E. Salman, “On-Chip Hybrid Regulator Topology for Portable SoCs with Near-Threshold Operation,” Proceedings of the IEEE Int. Symposium on Circuits and Systems, pp. 786-789, May 2016 (pdf)
  39. W. Liu, E. Salman, C. Sitik, and B. Taskin, “Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,” Proceedings of the IEEE Int. Symposium on Circuits and Systems, pp. 2595-2598, May 2016 (pdf)
  40. L. Filippini, E. Salman, and B. Taskin, “A Wirelessly Powered System with Charge Recovery Logic,” Proceedings of the IEEE International Conference on Computer Design, pp. 505-510, October 2015 (pdf)
  41. W. Liu, E. Salman, C. Sitik, and B. Taskin, “Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 283-288, May 2015 (pdf)
  42. M. Rathore, W. Liu, E. Salman, C. Sitik, and B. Taskin, “A Novel Static D Flip-Flop Topology for Low Swing Clocking,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 301-306, May 2015 (pdf)
  43. S. Fang and  E. Salman, “Low Swing TSV Signaling Using Novel Level Shifters with Single Supply Voltage,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1965-1968, May 2015 (pdf)
  44. W. Liu, E. Salman, C. Sitik, and B. Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1442-1445, May 2015 (pdf)
  45. H. Wang and E. Salman, “Resource Allocation Methodology for Through-Silicon-Vias and Sleep Transistors in 3D ICs,” Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 528-532, March 2015 (nominated for the best paper award) (pdf)
  46. H. Wang and E. Salman, “Enhancing System-Wide Power Integrity in 3D ICs with Power Gating,” Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 322-326, March 2015 (pdf)
  47. C. Sitik, L. Filipini, E. Salman, and B. Taskin, “High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 498-503, July 2014 (pdf)
  48. H. Wang, M. H. Asgari, and E. Salman, “Efficient Characterization of TSV-to-Transistor Noise Coupling in 3D ICs,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 71-76, May 2013 (pdf)
  49. S. M. Satheesh and E. Salman, “Effect of TSV Fabrication Technology on Power Distribution in 3D ICs,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 287-292, May 2013 (pdf)
  50.  H. Wang and E. Salman, “Power Gating Methodologies in TSV Based 3D Integrated Circuits,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 327-328, May 2013 (pdf)
  51. Z. Gan, E. Salman and M. Stanacevic, “Methodology to Determine Dominant Noise Source in a System-on-Chip Based Implantable Device,” IEEE International System-on-Chip Conference, pp. 115-119, September 2012 (pdf)
  52. S. M. Satheesh and E. Salman, “Design Space Exploration for Robust Power Delivery in TSV Based 3-D Systems-on-Chip,” Proceedings of the IEEE International System-on-Chip Conference, pp. 307-311, September 2012 (pdf)
  53. E. Salman, M. H. Asgari, and M. Stanacevic, “Signal Integrity Analysis of a 2-D and 3-D Integrated Potentiostat for Neurotransmitter Sensing,” Proceedings of the IEEE Biomedical Circuits and Systems Conference, pp. 17-20, November 2011 (pdf)
  54. E. Salman, “Noise Coupling Due to Through Silicon Vias (TSVs) in 3-D Integrated Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1411-1414, May 2011 (pdf)
  55. E. Salman, “Noise Management in Highly Heterogeneous SoC Based Integrated Circuits,” Proceedings of the IEEE International SoC Design Conference, pp. 1-4, November 2010 (invited paper) (pdf)
  56. R. Secareanu, O. Hartin, J. Feddeler, R. Moseley, J. Shepherd, B. Vrignon, J. Yang, Q. Li, H. Zhao, W. Li, L. Wei, E. Salman, R. Wang, D. Blomberg, and P. Parris, “Impact of Low-Doped Substrate Areas on the Reliability of Circuits Subject to EFT Events,” Proceedings of the IEEE International SoC Design Conference , pp. 21-24, November 2010 (pdf)
  57. R. Jakushokas, E. Salman, E. G. Friedman, R. M. Secareanu, O. L. Hartin, and C. Recker, “Compact Substrate Models for Efficient Noise Coupling and Signal Isolation Analysis,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2346-2349, May/June 2010 (pdf)
  58. E. Salman and E. G. Friedman, “Methodology to Achieve Higher Tolerance to Delay Variations in Synchronous Circuits,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 447-452, May 2010 (pdf)
  59. E. Salman and E. G. Friedman, “Reducing Delay Uncertainty in Deeply Scaled Integrated Circuits Using Interdependent Timing Constraints,” Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 77-82, March 2010 (pdf)
  60. Kose, E. Salman, and E. G. Friedman, “Shielding Methodologies in the Presence of Power/Ground Noise,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2277-2280, May 2009 (pdf)
  61. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, “Contact Merging Algorithm for Efficient Substrate Noise Analysis in Large Scale Circuits,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 9-14, May 2009 (pdf)
  62. S. Kose, E. Salman, Z. Ignjatovic, and E. G. Friedman, “Pseudo-Random Clocking to Enhance Signal Integrity,” Proceedings of the IEEE International System-on-Chip Conference, pp. 47-50, September 2008 (pdf)
  63. E. Salman and E. G. Friedman, “Methodology for Placing Localized Guard Rings to Reduce Substrate Noise in Mixed-Signal Circuits,” Proceedings of the 4th Conference on PhD Research in Microelectronics and Electronics, pp. 85-88, June 2008 (pdf)
  64. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, “Input Port Reduction for Efficient Substrate Extraction in Large Scale IC’s,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 376-379, May 2008 (pdf)
  65. E. Salman, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, “Equivalent Rise Time for Resonance in Power/Ground Noise Estimation,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2422-2425, May 2008 (pdf)
  66. E. Salman, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, “Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates,” Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 261-266, March 2008 (pdf)
  67. E. Salman, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, “Substrate Noise Reduction Based On Noise Aware Cell Design,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3227-3230, May 2007 (Invited paper to special session “The Future of Nanometer SoC Design – Grand Challenges and Opportunities”) (pdf)
  68. E. Salman, E. G. Friedman, and R. M. Secareanu, “Substrate and Ground Noise Interactions in Mixed-Signal Circuits,” Proceedings of the IEEE International System-on-Chip Conference, pp. 293-296, September 2006 (pdf)
  69. E. Salman, A. Dasdan, F. Taraporevala, K. Kucukcakar, and E. G. Friedman, “Pessimism Reduction in Static Timing Analysis Using Interdependent Setup and Hold Times,” Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 159-164, March 2006 (nominated for the best paper award) (pdf)
  70. E. Salman, H. Akin, O. Gursoy, A. Ergintav, I. Tekin, A. Bozkurt, and Y. Gurbuz, “Design of a 3.2 mW PLL Based Clock and Data Recovery Circuit in 90-nm CMOS Technology,” Proceedings of the Mediterranean Microwave Symposium, September 2005 (pdf)

Nonrefereed Publications and Reports

  1. W. Liu, C. Sitik, E. Salman, B. Taskin, S. Sundareswaran, and B. Huang, “Slew-Driven Clock Tree Synthesis (SLECTS) Methodology to Facilitate Low Voltage Clocking,” Semiconductor Research Corporation (SRC) Technology Conference (TECHCON), September 2016 (pdf)
  2. T. Wan, Y. Karimi, E. Salman, and M. Stanacevic, “A New Circuit Design Framework for IoT Devices,” Proceedings of the International Conference and Expo on Emerging Technologies for a Smarter World, October 2015
  3. W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran, and B. Huang, “Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies,” Semiconductor Research Corporation (SRC) Technology Conference (TECHCON), September 2015 (pdf)
  4. E. Salman and M. Stanacevic, “3-D Integrated Implantable Device for Deep Brain Sensing and Stimulation,” Proceedings of the International Conference and Expo on Emerging Technologies for a Smarter World, November 2011
  5. G. Bischof, B. Scholnick, and E. Salman, “Fully Integrated PLL Based Clock Generator for Implantable Biomedical Applications,” Proc. of the IEEE Annual Conference on Long Island Systems, Applications and Technology, May 2011
  6. E. Salman, A. Doboli, and M. Stanacevic, “Noise and Interference Management in 3-D Integrated Wireless Systems,” Proc. of the International Conference and Expo on Emerging Technologies for a Smarter World, September 2010

Ph.D. Dissertations

  1. I. Miketic, Hardware Security Techniques against Information Leakage and Counterfeiting in Integrated Circuits, PhD Dissertation, Stony Brook University, NY, August 2023 (pdf)
  2. K. Dhananjay, Detecting and Mitigating Hardware Security Attacks in Emerging Technologies and Applications, PhD Dissertation, Stony Brook University, NY, August 2022 (pdf)
  3. M. Rathore, Exploring the Accuracy vs. Energy Efficiency Trade-offs in Error-Aware Low Voltage DNN Accelerators, PhD Dissertation, Stony Brook University, Stony Brook, NY, August 2021 (pdf)
  4. M. Jain, Frontend Electronic System for a Triboelectric Harvester in a Smart Knee Implant, PhD Dissertation, Stony Brook University, Stony Brook, NY, May 2021 (pdf)
  5. T. Wan, AC Computing Methodology for Wirelessly Powered Devices, PhD Dissertation, Stony Brook University, Stony Brook, NY, December 2019 (pdf)
  6. C. Yan, Leveraging Monolithic Integrated Circuit Technology for Emerging Applications, PhD Dissertation, Stony Brook University, Stony Brook, NY, December 2018 (pdf)
  7. W. Liu, Low Voltage Clocking Methodologies for Nanoscale ICs, PhD Dissertation, Stony Brook University, Stony Brook, NY, January 2018 (pdf)
  8. Z. Gan, Design Methodologies to Manage Switching Noise with Applications to Biomedical Acoustic Systems, PhD Dissertation, Stony Brook University, Stony Brook, NY, August 2017 (pdf)
  9. H. Wang, Enhancing Power and Signal Integrity in Three-Dimensional Integrated Circuits, PhD Dissertation, Stony Brook University, Stony Brook, NY, January 2016 (pdf)

M.Sc. Theses

  1. B. Moy, Lightweight Encryption for Resource-Constrained Systems, Master’s Thesis, Stony Brook University, Stony Brook, NY, December 2020 (pdf)
  2. Y. Park, Fully Integrated Hybrid Voltage Regulator for Low Voltage Applications, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2016 (pdf)
  3. S. Panda, Investigating the Tolerance of Wirelessly Powered Charge-Recycling Logic to Power-Clock Phase Difference Deviations, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2016 (pdf)
  4. T. Noor, Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2016 (pdf)
  5. M. Rathore, Design and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2014 (pdf)
  6. P. Ji, Quantifying the Effect of Local Power Distribution Network and Vias on Power Integrity, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2013
  7. Z. Zhang, Comparative Analysis of Near-Threshold and Charge Recovery Circuits for Energy Efficiency and Performance, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2013 (pdf)
  8. A. Chandrasekhar, Critical Length Estimation for TSV-Based 3D Sub/Near-Threshold Circuits, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2013 (pdf)
  9. S. Mungi, MSc Thesis, Effective Distance Calculations for On-Chip Decoupling Capacitors in 3D ICs, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2013 (pdf)
  10. S. M. Satheesh, Power Distribution in TSV Based 3D Processor-Memory Stacks, Master’s Thesis, Stony Brook University, Stony Brook, NY, May 2012 (pdf)
  11. M. H. Asgari, TSV Related Noise Coupling in 3-D Integrated Circuits, Master’s Thesis, Stony Brook University, Stony Brook, NY, December 2011 (pdf)